View IBM03164B9C_3107051.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 120 features ? high performance: ? single pulsed ras interface ? fully synchronous to positive clock edge ? dual banks controlled by a11 (bank select) ? programmable cas latency: 1,2,3 ? programmable burst length: 1,2,4,8,full-page ? programmable wrap sequence: sequential or interleave ? multiple burst read with single write option ? automatic and controlled precharge command ? data mask for read/write control (x4, x8) ? dual data mask for byte control (x16) ? auto refresh (cbr), self refresh (sr) ? suspend mode and power down mode ? 4096 refresh cycles/64ms ? random column address every clk (1-n rule) ? single 3.3v 0.3v power supply ? supports lvttl i/o interface ? package: 44 pin 400 mil tsop-type ii (x4,x8) 50 pin 400 mil tsop-type ii (x16) 2-high stack tsoj description ibms 0316409c, 0316809c, and 0316169c are dual bank synchronous drams organized as 2mbit x 4 i/o x 2 bank, 1mbit x 8 i/o x 2 bank, and 512kbit x 16 i/o x 2 bank, respectively. these devices support lvttl i/o interface levels. a stacked version of the x 4 component is also offered. these synchronous devices achieve high speed data transfer rates of up to 125 mhz. the chip is fabricated with ibms advanced 16mbit cmos dram process technology. the device is designed to comply with all jedec standards set for synchronous dram prod- ucts, both electrically and mechanically. all of the control, address and data input/output circuits are synchronized with the positive edge of an externally supplied clock (clk). internal chip operating modes are defined by combinations of ras, cas, we, and cs and a com- mand decoder initiates the necessary timings for each operation. a twelve bit address bus accepts address data in the conventional ras/ cas multi- plexing style. eleven row addresses (a0-a10) and a bank select address (a11) are strobed with ras. ten column addresses (a0-a9) plus a10 and a bank select address (a11) are strobed with cas. column address a9 is dropped on the x8 device and column addresses a8 and a9 are dropped on the x16 device. access to the lower or upper dram in a stacked device is controlled by cs0 and cs1. prior to any access operation, the cas latency, burst length, and burst sequence must be pro- grammed into the device by address inputs a0-a11 during a mode register set cycle. in addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. operating the two memory banks in an inter- leave fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gapless data rate of up to 125 mhz is possible depending on burst length, cas latency, and speed grade of the device. auto refresh (cbr) and self refresh (sr) operation are supported. refreshing both decks of a stacked device simultaneously is allowed during self refresh but all other stacked device operations must be performed on a single deck at a time. -80 cl=3 -360 cl=3 -10 cl=3 units f ck clock frequency 125 100 100 mhz t ck clock cycle 8 10 10 ns t ac clock access time 6 5.5 8 ns . discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 120 08j3348.e35853 5/98 pin assignments for planar components (top view) pin description clk clock input dq0-dq15 data input/output cke clock enable dqm, ldqm, udqm data mask cs chip select vdd power (+3.3v) ras row address strobe vss ground cas column address strobe vddq power for dqs (+3.3v) we write enable vssq ground for dqs a11 (bs) bank select nc no connection a0 - a10 address inputs 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 44 43 42 41 40 39 36 35 34 33 32 31 38 37 30 29 28 27 26 25 24 23 vdd dq0 vssq dq1 vddq dq2 vddq nc nc we cas ras vssq dq3 cs a11(bs) a10 a0 a1 a2 a3 vdd v ss dq7 vssq dq6 vddq dq5 vddq nc nc dqm clk cke vssq dq4 nc a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 50 49 48 47 46 45 42 41 40 39 38 37 44 43 36 35 34 33 32 31 30 29 vdd dq0 dq1 vssq dq2 dq3 dq5 vssq dq6 dq7 vddq ldqm vddq dq4 we cas ras cs a11(bs) a10 a0 v ss dq15 dq14 vssq dq13 dq12 dq10 vssq dq9 dq8 vddq nc vddq dq11 udqm clk cke nc a9 a8 a7 23 24 25 28 27 26 a1 a2 a3 vdd a6 a5 a4 v ss 50-pin plastic tsop(ii) 400 mil 512kbit x 16 i/o x 2 bank ibm0316169ct3 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 44 43 42 41 40 39 36 35 34 33 32 31 38 37 30 29 28 27 26 25 24 23 vdd nc vssq dq0 vddq nc vddq nc nc we cas ras vssq dq1 cs a11(bs) a10 a0 a1 a2 a3 vdd v ss nc vssq dq3 vddq nc vddq nc nc dqm clk cke vssq dq2 nc a9 a8 a7 a6 a5 a4 v ss 44-pin plastic tsop(ii) 400 mil 2mbit x 4 i/o x 2 bank ibm0316409ct3 44-pin plastic tsop(ii) 400 mil 1mbit x 8 i/o x 2 bank ibm0316809ct3 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 120 pin assignments for 2-high stack package (dual cs pins) (top view) pin description clk clock input dq0-dq3 data input/output cke clock enable dqm data mask cs0, cs1 chip select vdd power (+3.3v) ras row address strobe vss ground cas column address strobe vddq power for dqs (+3.3v) we write enable vssq ground for dqs a11 (bs) bank select nc no connection a0 - a10 address inputs 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 44 43 42 41 40 39 36 35 34 33 32 31 38 37 30 29 28 27 26 25 24 23 vdd nc vssq dq0 vddq nc vddq nc nc we cas ras vssq dq1 * cs0/nc a11 (bs) a10 a0 a1 a2 a3 vdd v ss nc vssq dq3 vddq nc vddq nc nc dqm clk cke vssq dq2 nc/ cs1 * a9 a8 a7 a6 a5 a4 v ss 44-pin plastic tsoj(ii) 400 mil (2mbit x 4 i/o x 2 bank) x 2 high IBM03164B9Ct3 * cs0 selects the lower dram in the stack. * cs1 selects the upper dram in the stack. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 120 08j3348.e35853 5/98 input/output functional description symbol type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low. by deacti- vating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. cs, cs0, cs1 input pulse active low cs ( cs0, cs1 for stacked devices) enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new com- mands are ignored but previous operations continue. ras, cas we input pulse active low when sampled at the positive rising edge of the clock, cas, ras, and we define the operation to be executed by the sdram. a11 (bs) input level selects which bank is to be active. a11 low selects bank a and a11 high selects bank b. a0 - a10 input level during a bank activate command cycle, a0-a10 defines the row address (ra0-ra10) when sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address (ca0-ca9) when sampled at the rising clock edge. a10 is used to invoke auto-precharge operation. if a10 is high, auto-precharge is selected and a11 defines the bank to be precharged (low=bank a, high=bank b). if a10 is low, auto-precharge is disabled. during a precharge command cycle, a10 is used in conjunction with a11 to control which bank(s) to precharge. if a10 is high, both bank a and bank b will be precharged regardless of the state of a11. if a10 is low, then a11 is used to define which bank to precharge. dq0 - dq15 input output level data input/output pins operate in the same manner as on conventional drams. dqm ldqm udqm input pulse active low the dq mask (dqm) places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers consistent with an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write opera- tion if dqm is high. vdd, v ss supply power and ground for the input buffers and the core logic. vddq, vssq supply isolated power supply and ground for the output buffers to provide improved noise immu- nity. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 120 ordering information - planar devices (single cs pin) part number cas latencies i/o width i/o type package power supply clock cycle ibm0316409ct3d-80 2,3 x4 lvttl 400mil type ii tsop-44 3.3v 8ns ibm0316409ct3d-10 1,2,3 x4 lvttl 400mil type ii tsop-44 3.3v 10ns ibm0316809ct3d-80 2,3 x8 lvttl 400mil type ii tsop-44 3.3v 8ns ibm0316809ct3d-360 2,3 x8 lvttl 400mil type ii tsop-44 3.3v 10ns ibm0316809ct3d-10 1,2,3 x8 lvttl 400mil type ii tsop-44 3.3v 10ns ibm0316169ct3d-80 2,3 x16 lvttl 400mil type ii tsop-50 3.3v 8ns ibm0316169ct3d-10 1,2,3 x16 lvttl 400mil type ii tsop-50 3.3v 10ns ordering information - 2 high stacked devices (dual cs pins) part number cas latencies i/o width i/o type package power supply clock cycle IBM03164B9Ct3d-10 1,2,3 x4 lvttl 400mil type ii tsoj-44 2-high 3.3v 10ns discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 120 08j3348.e35853 5/98 block diagram (2mbit x 4 i/o x 2 bank) dq1 dq2 dq0 dq3 data input/output buffers cke buffer clk buffer cs buffer ras buffer cas buffer we buffer dqm buffer cke clk cs ras cas dqm we command decoder mode register refresh clock row address counter self a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 (bs) 12 12 2048 sequential control bank a row/column select bank a predecode a 8 data latches column decoder and dq gate sense ampli?ers 1024 memory bank a 2048 x 1024 2048 row decoder 8 sequential control bank b predecode b 8 data latches column decoder and dq gate sense ampli?ers 1024 memory bank b 2048 x 1024 2048 row decoder 8 address buffers (12) row/column select bank b 3 11 3 11 11 4 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 120 block diagram (1mbit x 8 i/o x 2 bank) dq1 dq2 dq0 dq3 dq5 dq6 dq4 dq7 data latches data latches 8 8 column decoder and dq gate sense ampli?ers data input/output buffers 8 cke buffer clk buffer cs buffer ras buffer cas buffer we buffer dqm buffer cke clk cs ras cas dqm we command decoder mode register refresh clock row address counter self a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 (bs) 12 12 sequential control bank a row/column select bank a predecode a column decoder and dq gate sense ampli?ers sequential control bank b predecode b 8 address buffers (12) row/column select bank b 3 11 3 11 11 data latches 8 column decoder and dq gate sense ampli?ers 512 memory bank b 2048 x 1024 memory bank b 2048 x 512 2048 row decoder row decoder 8 8 8 8 8 8 8 1024 512 memory bank a 2048 x 512 2048 row decoder row decoder discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 120 08j3348.e35853 5/98 block diagram (512kbit x 16 i/o x 2 bank) dq1 dq2 dq0 dq3 dq5 dq6 dq4 dq7 dq9 dq10 dq8 dq11 dq13 dq14 dq12 dq15 column decoder and dq gate sense ampli?ers data latches data latches 8 8 column decoder and dq gate sense ampli?ers column decoder and dq gate sense ampli?ers 1024 512 memory bank a 2048 x 512 row decoder row decoder data latches data latches 8 8 column decoder and dq gate sense ampli?ers 8 cke buffer clk buffer cs buffer ras buffer cas buffer we buffer dqm buffer cke clk cs ras cas udqm we command decoder mode register refresh clock row address counter self a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 (bs) 12 12 sequential control bank a row/column select bank a predecode a column decoder and dq gate sense ampli?ers sequential control bank b predecode b 8 address buffers (12) row/column select bank b 3 11 3 11 11 16 16 16 16 16 16 1024 256 memory bank a 2048 x 256 2048 row decoder row decoder data latches data latches 8 column decoder and dq gate sense ampli?ers 256 memory bank b 2048 x 1024 memory bank b 2048 x 512 memory bank b 2048 x 1024 memory bank b 2048 x 256 2048 row decoder row decoder row decoder row decoder data input/output buffers dqm buffer ldqm 16 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 120 block diagram (2mbit x 4 i/o x 2 bank) x 2-high dq1 dq2 dq0 dq3 cke clk a10-a0 ras a11(bs) cas we dqm 2mb x 4 i/o x 2 bank cs0 cs1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 120 08j3348.e35853 5/98 power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined man- ner. during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage no later than any of the input signal voltages. the power on voltage must not exceed vdd+0.3v on any of the input pins or vdd supplies. after power on, an initial pause of 100 m s is required followed by a precharge of both banks using the precharge command. to reduce the possibility of data contention on the dq bus during power on, it is recommended that the dqm pin(s) be held high during the initial pause period. once both banks have been precharged, a minimum of two auto refresh cycles (cbr) must occur before the mode register can be programmed. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register for application flexibility, cas latency, burst length, burst sequence, and operation type are user defined vari- ables and must be programmed into the sdram mode register with a single mode register set command. contents of the mode register can be altered by re-executing the mode register set command. if the user chooses to modify only a subset of the mode register variables, all variables must be redefined when the mode register set command is issued. after initial power up, the mode register set command must be issued before read or write cycles may begin. both banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of ras, cas, cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued on the second clock following the mode register set command. cas latency cas latency is a parameter that is used to define the delay from when a read command is registered on a rising clock edge to when the data from that read command becomes available at the outputs. cas latency is expressed in terms of clock cycles and can be programmed to a value of 1, 2, or 3 cycles. the value of cas latency is determined by the speed grade of the device and the clock frequency that is used in the appli- cation. a table showing the relationship between the cas latency, speed grade, and clock frequency appears in the electrical characteristics section of this document. once the appropriate cas latency has been selected it must be programmed into the mode register after power up. for an explanation of this procedure, see programming the mode register in the previous section. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 120 mode register operation (address input for mode set) bs a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register (mx) cas latency m6 m5 m4 latency 0 0 0 reserved 001 1 010 2 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved burst length m2 m1 m0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved burst type m3 type 0 sequential 1 interleave operation mode m11 m10 m9 m8 m7 mode 0 0 0 0 0 normal x x 100 multiple burst with single write operation mode discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 120 08j3348.e35853 5/98 burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). there are three parameters that define how the burst mode will operate. these parameters include burst sequence, burst length, and operation mode. the burst sequence and burst length are programmable, and are determined by address bits a0 - a3 during the mode register set com- mand. operation mode is also programmable and is set by address bits a7 - a10 and bs. the burst type is used to define the order in which the burst data will be delivered or stored to the sdram. two types of burst sequences are supported, sequential and interleaved. see table. the burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. the burst length can be programmed to have values of 1, 2, 4, 8 or full page (actual page length is dependent on organization: x4, x8, or x16). full page burst operation is only pos- sible using the sequential burst type. burst operation mode can be normal operation or multiple burst with single write operation. normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. multiple burst with single write operation was added to support write through cache oper- ation. here, the programmed burst length only applies to read cycles. all write cycles are single write opera- tions when this mode is selected. note: page length is a function of i/o organization and column addressing. x4 organization (ca0-ca9); page length = 1024 bits x8 organization (ca0-ca8); page length = 512 bits x16 organization (ca0-ca7); page length = 256 bits burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page (note) n n n cn, cn+1, cn+2, ...... not supported discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 120 bank activate command in relation to the operation of a fast page mode dram, the bank activate command corresponds to a falling ras signal. the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank select address, a11 (sometimes referred to as bs), is used to select the desired bank. if bs is low then bank a is activated, if bs is high then bank b is activated. the row address a0 - a10 is used to determine which row to activate in the selected bank. only banks a and b within a single deck of a 2-high stacked device can be accessed. simultaneous operation of both decks in a stacked device is not allowed, except during self refresh. the bank activate command must be applied before any read or write operation can be executed. the delay from when the bank activate command is applied to when the first read or write operation can begin must meet or exceed the ras to cas delay time (t rcd ). once a bank has been activated it must be pre- charged before another bank activate command can be applied to the same bank. the minimum time inter- val between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). bank activate command cycle ( cas latency = 3, t rcd = 3 ) address clk t0 t2 t1 t3 tn tn+1 tn+2 tn+3 command nop nop nop nop bank a row addr. bank a activate write a with auto- bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate ras- cas delay ( t rcd ) : h or l ras cycle time ( t rc ) precharge ras - ras delay time ( t rrd ) bank b row addr. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 120 08j3348.e35853 5/98 read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras high and cas low at the clocks rising edge after the necessary ras to cas delay (t rcd ). we must also be defined at this time to determine whether the access cycle is a read operation ( we high), or a write operation ( we low). the sdram provides a wide variety of fast access modes. a single read or write command will initiate a serial read or write operation on successive clock cycles at data rates of up to 125 mhz. the number of serial data bits for each access is equal to the burst length, which is programmed into the mode register. although the burst length is user programmable, the boundary of the burst cycle is restricted to specific segments of the page length. for example, the 2mbit x 4 i/o x 2 bank device has a page length of 1024 bits (defined by ca0-ca9). if a burst length of 4 is programmed into the mode register, then the page length is divided into 256 uniquely addressable boundary segments (4-bits each). a 4-bit burst operation will occur entirely from one of the 256 groups beginning with the column address supplied to the device during the read or write command (ca0- ca9). the second, third, and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, the burst sequence, and burst boundary. the above discussion does not apply when full page burst is programmed into the mode register. full page burst operation is only allowed for the sequential burst sequence and has no address boundaries. the sdram device will continue bursting data even after all locations of the page have been accessed. the burst sequence will start at the column address defined during the read or write cycle and will increment sequen- tially until the highest order column address has been reached. at this point, the burst counter will reset to address 0 and continue to perform burst read or burst write operations sequentially until either a burst stop command is issued, a precharge command is issued to the bursting bank, or until a new read or write command is issued. similar to page mode of conventional drams, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. the refresh period (t ref ) is what limits the number of random col- umn accesses to an activated bank. a new burst access can be done even before the previous burst ends. the ability to interrupt a burst operation at every clock cycle is supported, this is referred to as the 1-n rule. when the previous burst is interrupted by another read or write command, the remaining addresses are overridden by the new address once the cas latency has been satisfied. precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. to perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new bank activate command must be issued. when both bank a and bank b are acti- vated, interleaved (ping pong) bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between the two banks, fast and seamless data access operation among many different pages can be realized. when the two banks are activated, column to column interleave operation can be done between two different pages. finally, read or write commands can be issued to the same bank or between active banks on every clock cycle. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 120 burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst, the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the cas latency that is set in the mode register. burst read operation (burst length = 4, cas latency = 1, 2, 3) command read a nop nop nop nop nop nop nop dout a 0 cas latency = 1 t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 dout a 1 dout a 2 dout a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck1, dqs dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 120 08j3348.e35853 5/98 read interrupted by a read a burst read may be interrupted before completion of the burst by another read command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. when a burst read operation is interrupted, the remaining addresses of the current burst cycle are overridden starting with the new column address applied with the interrupting read command. the data from the first read command continues to appear on the dqs until the cas latency of the interrupting read command is satis- fied. at this point, the data from the interrupting read command will appear on the dqs and continue for the full burst length. read interrupted by a read (burst length = 4, cas latency = 1, 2, 3) command read a read b nop nop nop nop nop nop t ck1, dqs cas latency = 1 t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 120 read interrupted by a write to interrupt a burst read with a write command, dqm must be used to avoid data contention on the data bus by placing the chip output drivers in a high impedance state at least one clock cycle before the write com- mand is initiated. to insure the chip output drivers are tri-stated one cycle before the write operation begins, dqm must be activated at least 3 clock cycles before the write command and be deactivated in the same clock cycle as the write command. read interrupted by a write (burst length = 4, cas latency = 1, 2, 3) command read a nop nop write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 t ck3 , dqs cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop din a 0 din a 1 din a 2 din a 3 t ck2 , dqs cas latency = 2 dout a 0 dout a 1 dout a 0 : h or l must be hi-z before the write command nop din a 0 din a 1 din a 2 din a 3 t ck1 , dqs cas latency = 1 dout a 1 dout a 2 dout a 0 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 120 08j3348.e35853 5/98 burst write command the burst write command is initiated by having cs, cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. there is no cas latency required for burst write cycles. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaining data inputs must be supplied on each subse- quent rising clock edge until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. write interrupted by a write a burst write operation may be interrupted before completion of the burst. when a burst write cycle is inter- rupted by a new write command, the remaining addresses of the initial write cycle are overridden starting with the new column address applied with the interrupting write command. data will be written into the device until the programmed burst length of the last write command is satisfied. burst write operation (burst length = 4, cas latency = 1, 2, 3) write interrupted by a write (burst length = 4, cas latency = 1, 2, 3) command nop write a nop nop nop nop nop nop dqs din a 0 din a 1 din a 2 din a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is masked. the first data element and the write are registered on the same clock edge. dont care command nop write a write b nop nop nop nop nop dqs din a 0 din b 0 din b 1 din b 2 nop din b 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 1 clk interval discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 120 write interrupted by a read a read command will interrupt a burst write operation on the same clock cycle that the read command is registered. the dqs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. when the read command is registered, any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the read command is initiated will actually be written to the memory. write interrupted by a read (burst length = 4, cas latency = 1, 2, 3) command nop write a read b nop nop nop nop nop nop t ck1, dqs cas latency = 1 din a 0 t ck2, dqs cas latency = 2 din a 0 t ck3, dqs cas latency = 3 din a 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. input data must be removed from the dqs at least one clock cycle before the read data appears on the outputs to avoid data contention. dont care dont care dont care dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 120 08j3348.e35853 5/98 burst stop command once a burst read or write operation has been initiated, there exist several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, using a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. the burst stop command is defined by having ras and cas high with cs and we low at the rising edge of the clock. when using the burst stop command during a burst read cycle, the data dqs go to a high imped- ance state after a delay which is equal to the cas latency set in the mode register. when a burst stop command is issued during a burst write operation, only data presented prior to the burst stop command will be written into the device. any data presented to the device coincident with the burst stop command or later will be ignored. termination of a burst read operation (burst length > 4, cas latency = 1, 2, 3 ) command read a nop nop nop burst nop nop nop nop t ck1, dqs cas latency = 1 t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 the burst ends after a delay equal to the cas latency. dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 the bank remains activated. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 120 auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the pre- charge command or the auto-precharge function. when a read or a write command is given to the sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto-precharge function is engaged. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge immediately and may finish before all burst read cycles have been completed. this feature allows the precharge operation to be partially or com- pletely hidden during the burst read cycles (dependent upon burst length) thus improving system perfor- mance for random data access. auto-precharge can also be implemented during write commands. a read or write command without auto-precharge can be terminated in the midst of a burst operation. how- ever, a read or write command with auto-precharge can not be interrupted by a command to the same bank. therefore use of a read, write, precharge, or burst stop command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. if a10 is high when a read command is issued, the read with auto-precharge function is initiated. once the precharge operation has started the bank cannot be reactivated until an asynchronous delay time equal to t rp + t dpl, expressed in nanoseconds rather than clocks, has been satisfied. it should be noted that the device will not respond to the auto-precharge command if the device is programmed for full page burst read or write cycles. termination of a burst write operation (burst length =x, cas latency = 1, 2, 3) command nop write a nop nop burst nop nop nop nop din a 0 din a 1 din a 2 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. dqs cas latency = 1,2,3 dont care discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 120 08j3348.e35853 5/98 although a read command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a read or write command to the other bank. the auto-precharge function will begin normally with the issuing command. burst read with auto-precharge (burst length = 4) burst read w/ auto-precharge interrupted by read (burst length = 4, cas latency = 2, 3) command nop nop nop nop read a auto-precharge t rp + t dpl clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop * * dqs t ck2 dqs t ck3 begin auto-precharge. dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 nop nop nop t rp * + t dpl bank can be reactivated after completion of t rp + t dpl . * for auto-precharge, this is an asynchronous delay which may complete prior to a clock edge,depending on t rp , t dpl and t ck . the bank cannot be reactivated until the rising clock edge following the completion of the delay. * t rp , t rcd = 2 clocks for -360 command nop nop nop nop read a auto-precharge clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop * t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 begin auto-precharge a bank can be reactivated at completion of t rp + t dpl dout a 0 dout a 1 nop dout a 0 dout a 1 dout b 0 dout b 1 read b dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 t rp + t dpl * t rp * + t dpl * * t rp , t rcd = 2 clocks for-360 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 120 if interrupting a read command with auto-precharge with a write command, dqm must be used to avoid dq contention. if a10 is high when a write command is issued, the write with auto-precharge function is initiated. the bank undergoing auto-precharge can not be reactivated until t dpl and t rp are satisfied. this is referred to as t dal, data-in to active delay (t dal = t dpl + t rp ), and is an asynchronous delay time during auto-precharge . burst read with auto-precharge interrupted by write (burst length = 8, cas latency = 2) burst write with auto-precharge (burst length = 2) command nop nop nop read a auto-precharge clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop * t ck2, dqs cas latency = 2 dqm begin auto-precharge a bank a can be reactivated at completion of t rp + t dpl nop dout a 0 dout b 0 dout b 1 write b dout b 2 dout b 3 nop dout b 4 t rp + t dpl * din a 0 command nop nop nop nop write a auto-precharge din a 1 t dal clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop din a 0 din a 1 t dal * * dqs t ck2 dqs t ck3 bank can be reactivated after completion of t dal . * nop nop nop begin auto-precharge. for auto-precharge, t dal is an asynchronous delay which may complete prior to a clock edge, depending on t rp , t dpl and t ck . the bank cannot be reactivated until the rising clock edge following the delay. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 120 08j3348.e35853 5/98 similar to the read command, a write command with auto-precharge can not be interrupted by a command to the same bank. it can be interrupted by a read or write command to the other bank, however. the auto- precharge function is unaffected by the interrupting command and will begin as normally scheduled according to burst length. burst write with auto-precharge interrupted by write (burst length = 4, cas latency = 3) burst write with auto-precharge interrupted by read (burst length = 4, cas latency = 3) din a 0 command nop nop nop write a auto-precharge din a 1 t dal clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop t ck3, dqs cas latency = 3 begin auto-precharge bank a can be reactivated at completion of t dal * write b din b 0 din b 1 din b 2 din b 3 * t rp , t dpl = 2 clocks for-360 * nop nop nop din a 0 command nop nop nop write a auto-precharge din a 1 t dal clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop * t ck3, dqs cas latency = 3 begin auto-precharge bank a can be reactivated at completion of t dal * read b din a 2 nop dout b 0 dout b 1 dout b 2 * t rp , t dpl = 2 clocks for-360 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 25 of 120 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge com- mand is triggered when cs, ras and we are low and cas is high at the rising edge of the clock. the pre- charge command can be used to precharge each bank separately or both banks simultaneously. two address bits a10 and a11 (bs) are used to define which bank(s) is to be precharged when the command is issued. for read cycles, the precharge command may be applied consistent with the cas latency set in the mode register. the data dqs go to a high impedance state after a delay which is equal to the latency, similar to a burst stop command. refer to the following figures. for write cycles, however, a delay must be satisfied from the start of the last burst write cycle until the pre- charge command can be issued. this delay is known as t dpl , data-in to precharge delay. after the precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). bank selection for precharge by address bits a10 bs(a11) precharged bank(s) low low bank a only low high bank b only high dont care both banks a and b burst read followed by precharge command (burst length = 4, cas latency = 2) command read ax 0 nop nop nop nop nop nop nop t ck2, dqs cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a * bank can be reactivated at completion of t rp . * t rp discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 26 of 120 08j3348.e35853 5/98 burst read followed by precharge command (burst length = 4, cas latency = 3) burst read followed by precharge command (burst length = 4, cas latency = 3) command read ax 0 nop nop nop nop nop nop nop t ck3, dqs cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a * bank can be reactivated at completion of t rp . * t rp (-80,-10) command read ax 0 nop nop nop nop nop nop nop t ck3, dqs cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a * bank can be reactivated at completion of t rp . * t rp ( -360 ) discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 27 of 120 burst write followed by precharge command (burst length = 2, cas latency = 2) command nop precharge a nop nop write ax 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 0 din ax 1 bank can be reactivated at completion of t dal ( t dpl + t rp ). * activate bank ax t ck2, dqs cas latency = 2 t dpl * t dal t rp discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 28 of 120 08j3348.e35853 5/98 burst write followed by precharge command (burst length = 2, cas latency = 3) command nop precharge a nop nop write ax 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 0 din ax 1 bank can be reactivated at completion of t dal ( t dpl + t rp ). * activate bank ax t ck3 , dq s cas latency=3 t dpl * t dal t rp (-80, -10) command nop nop nop write ax 0 nop nop nop din ax 0 din ax 1 activate bank ax t ck3 , dqs cas latency=3 t dpl t dal t rp ( -360 ) t 9 precharge a * discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 29 of 120 precharge termination the precharge command may be used to terminate either a burst read or burst write operation. when the precharge command is issued, the burst operation is terminated and bank precharge begins. for burst read operations, valid data will continue to appear on the data bus as a function of cas latency. burst read interrupted by precharge (burst length = 8, cas latency = 1) burst read interrupted by precharge (burst length = 8, cas latency = 2) t rp command nop read ax 0 nop nop nop nop nop t ck1, dqs cas latency = 1 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 * * bank can be reactivated at completion of t rp . nop precharge a burst is terminated one clock after the precharge command, consistent with cas latency. t rp command read ax 0 nop nop nop nop nop nop t ck2, dqs cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 precharge a * nop burst is terminated two clocks after the precharge command, * bank can be reactivated at completion of t rp . consistent with cas latency. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 30 of 120 08j3348.e35853 5/98 burst read interrupted by precharge (burst length = 8, cas latency = 3) burst read interrupted by precharge (burst length = 8, cas latency = 3) command read ax 0 nop nop nop nop nop nop t ck3, dqs cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 nop * * bank can be reactivated at completion of t rp . precharge a burst is terminated three clocks after the precharge command, t rp consistent with cas latency. dout ax 3 (-80, -10) command read ax 0 nop nop nop nop nop nop t ck3, dqs cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 nop * * bank can be reactivated at completion of t rp . precharge a burst is terminated three clocks after the precharge command, t rp consistent with cas latency. ( -360 ) dqm dout ax 3 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 31 of 120 burst write operations will be terminated by the precharge command. however, write data written to the device prior to the precharge command may be stored incorrectly and is a function of cas latency and t dpl . when cas latency is set to equal 1 or 2 or when set to 3 with t dpl = 1 clock, the last write data that will be properly stored in the device is that write data that is presented to the device on the clock cycle prior to the precharge command. the write data presented during the precharge command will not be written. precharge termination of a burst write (burst length = 8, cas latency = 1) precharge termination of a burst write (burst length = 8, cas latency = 2) command nop precharge a nop nop write ax 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 1 din ax 2 bank can be reactivated at completion of t dal * t dpl * t dal din ax 0 t ck1, dqs cas latency = 1 nop t rp command nop precharge a nop nop write ax 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 1 din ax 2 bank can be reactivated at completion of t dal . * t dpl * din ax 0 t ck2, dqs cas latency = 2 nop t rp t dal discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 32 of 120 08j3348.e35853 5/98 when cas latency is set to equal 3 and t dpl = 2 clocks, the last write data that will be properly stored in the device is that write data that is presented to the device two clocks prior to the precharge command. the write data presented during the clock cycle prior to the precharge command may be stored incorrectly. to prevent the writing of invalid data to the device, dqm must be asserted high one clock cycle prior to the precharge command to mask the invalid write data. precharge termination of a burst write (burst length = 8, cas latency = 3) precharge termination of a burst write (burst length = 8, cas latency = 3) command nop precharge a nop nop write ax 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 1 bank can be reactivated at completion of t dal . * din ax 0 t ck3, cas latency = 3 nop dqs t dpl t rp din ax 2 * t dal (-80, -10) command nop precharge a nop nop write ax 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 1 bank can be reactivated at completion of t dal . t dpl * din ax 0 dqm dqm is needed to mask the invalid data t ck3, cas latency = 3 nop t rp t dal dqs * ( -360 ) discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 33 of 120 automatic refresh command ( cas before ras refresh) when cs, ras and cas are held low with cke and we high at the rising edge of the clock, the chip enters the automatic refresh mode (cbr). both banks of the sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the auto refresh command (cbr) can be applied. for a stacked device, only one deck at a time can be refreshed using automatic refresh mode. an address counter, internal to the device, supplies the bank address during the refresh cycle. no control of the external address pins is required once this cycle has started. when the refresh cycle has completed, both banks of the sdram will be in the precharged (idle) state. a delay between the auto refresh command (cbr) and the next activate command or subsequent auto refresh command must be greater than or equal to the ras cycle time (t rc ). self refresh command the sdram device has a built-in timer to accommodate self refresh operation. the self refresh command is defined by having cs, ras, cas and cke held low with we high at the rising edge of the clock. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the user may halt the external clock while the device is in self refresh mode, however, the clock must be restarted before the device can exit self refresh operation. once the clock is cycling, the exit command will be registered asynchronously by bringing cke high. after cke is brought high, an internal timer is started to insure cke is held high for approximately 10ns before registering the self refresh exit command. the purpose of this circuit is to filter out noise glitches on the cke input which may cause the sdram to erroneously exit self refresh operation. once the self refresh command is registered, a delay equal to the ras cycle time (t rc ) must be satisfied before any new command can be issued to the device. cke must remain high for the entire self refresh exit period (t srex ) and commands must be gated off with cs held high. alternatively, nop commands may be registered on each positive clock edge during the self refresh exit interval. (see self refresh exit figures.) when using self refresh, both decks of a stacked device may be refreshed at the same time. self refresh exit (commands gated off with cs high) clk t m t m+2 t m+1 t m+3 t m+4 t m+5 t m+6 t m+7 t m+8 command cke : h or l begin self refresh exit cs self refresh exit command t rc any self refresh exit command discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 34 of 120 08j3348.e35853 5/98 data mask the sdram has a data mask function that can be used in conjunction with data read and write cycles. when the data mask is high during a write cycle, the write operation is prohibited immediately (zero clock latency). if the data mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two clock delay, independent of cas latency. self refresh exit (commands gated off with nop commands) data mask activated during a read cycle (burst length = 4, cas latency = 1) clk t m t m+2 t m+1 t m+3 t m+4 t m+5 t m+6 t m+7 t m+8 command cke : h or l begin self refresh exit cs self refresh exit command t rc any self refresh exit command nop nop nop nop nop nop nop command nop read a nop nop nop nop nop nop nop dqm : h or l a two clock delay before the dqs become hi-z dqs clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 35 of 120 no operation command the no operation command should be used in cases when the sdram is in a idle or a wait state. the pur- pose of the no operation command is to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras, cas, and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras, cas, and we signals become dont cares. power down mode in order to reduce standby power consumption, two power down modes are available: precharge and active power down mode. to enter precharge power down mode, all banks must be precharged and the neces- sary precharge delay (t rp ) must occur before the sdram can enter the power down mode. if a bank is acti- vated but not performing a read or write operation, active power down mode will be entered. (issuing a power down mode command when the device is performing a read or write operation causes the device to enter clock suspend mode. see the following section.) once the power down mode is initiated by holding cke low, all of the receiver circuits except clk and cke are gated off. the power down mode does not per- form any refresh operations, therefore the device cant remain in power down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing cke high. a one clock delay after the registration of cke high is required for the sdram to exit the power down mode. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 36 of 120 08j3348.e35853 5/98 clock suspend mode during normal access mode, cke is held high enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the inter- nal clock and suspends or freezes any clocked operation that was currently being executed. there is a one clock delay between the registration of cke low and the time at which the sdrams operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bringing cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited. when the operation of the sdram is suspended during the execution of a burst read operation, the last valid data output onto the dq pins will be actively held valid until clock suspend mode is exited. if clock suspend mode is initiated during a burst write operation, then the input data is masked and ignored until the clock suspend mode is exited. clock suspend during a read cycle (burst length = 4, cas latency = 2) clock suspend during a write cycle (burst length = 4, cas latency = 2) clk t0 t2 t1 t3 t4 t5 t6 t7 t8 command nop read a nop nop nop nop cke dqs dout a 0 dout a 2 dout a 1 : h or l a one clock delay before suspend operation starts a one clock delay to exit the suspend command dout element at the dqs when the suspend operation starts is held valid clk t0 t2 t1 t3 t4 t5 t6 t7 t8 command nop write a nop nop nop nop cke dqs din a 2 din a 3 : h or l a one clock delay before suspend operation starts a one clock delay to exit the suspend command din is masked during the clock suspend period din a 1 din a 0 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 37 of 120 command truth table (notes: 1) function cke cs ras cas we dqm a11 a10 a9 - a0 notes previous cycle current cycle mode register set h x l l l l x op code auto (cbr) refresh h h l l l h x x x x entry self refresh h l l l l h x x x x exit self refresh l h h x x x x x x x single bank precharge h x l l h l x bs l x 2 precharge all banks h x l l h l x x h x bank activate h x l l h h x bs row address 2 write h x l h l l x bs l column 2 write with auto-precharge h x l h l l x bs h column 2 read h x l h l h x bs l column 2 read with auto-precharge h x l h l h x bs h column 2 burst termination h x l h h l x x x x 3 no operation h x l h h h x x x x device deselect h x h x x x x x x x clock suspend/standby mode l x x x x x x x x x 4 data write/output enable h x x x x x l x x x 5 data mask/output disable h x x x x x h x x x 5 power down mode entry x l x x x x x x x x 6, 7 power down mode exit x h x x x x x x x x 6, 7 1. all of the sdram operations are defined by states of cs, we, ras, cas, and dqm at the positive rising edge of the clock. for stacked devices: only one deck can be operated at once, except during self refresh. 2. bank select (bs), if bs = 0 then bank a is selected, if bs = 1 then bank b is selected. 3. during a burst write cycle there is a zero clock delay, for a burst read cycle the delay is equal to the cas latency. 4. during normal access mode, cke is held high and clk is enabled. when it is low, it freezes the internal clock and extends dat a read and write operations. one clock delay is required for mode entry and exit. 5. the dqm has two functions for the data dq read and write operations. during a read cycle, when dqm goes high at a clock tim- ing the data outputs are disabled and become high impedance after a two clock delay. dqm also provides a data mask function for write cycles. when it activates, the write operation at the clock is prohibited (zero clock latency). 6. all banks must be precharged before entering the precharge power down mode. if banks are active, active power down mode is entered. the power down mode does not perform any refresh operations, therefore the device cant remain in this mode longer than the refresh period (t ref ) of the device. one clock delay is required for mode entry and exit. 7. if cs is low, then when cke returns high, no command is registered into the chip for one clock cycle. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 38 of 120 08j3348.e35853 5/98 clock enable (cke) truth table current state cke command action notes previous cycle current cycle cs ras cas we a11 a10 - a0 self refresh h x xxxxx x invalid 1 l h h x x x x x exit self refresh with device deselect 2 l h l h h h x x exit self refresh with no operation 2 l h l h h l x x illegal 2 l h l h l x x x illegal 2 l h l l x x x x illegal 2 l l xxxxx x maintain self refresh power down h x xxxxx x invalid 1 l h h x x x x x power down mode exit, all banks idle 2 l h l x x x x x illegal 2 l l xxxxx x maintain power down mode all banks idle h h hxxx refer to the idle state section of the current state truth table 3 hhlhxx 3 hhllhx 3 h h l l l h x x cbr refresh h h l l l l op code mode register set 4 h l hxxx refer to the idle state section of the current state truth table 3 hllhxx 3 hlllhx 3 h l l l l h x x entry self refresh 4 h l l l l l op code mode register set l x xxxxx x power down 4 any state other than listed above h h xxxxx x refer to operations in the current state truth table h l xxxxx x begin clock suspend next cycle 5 l h xxxxx x exit clock suspend next cycle l l xxxxx x maintain clock suspend 1. for the given current state, cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other inputs are re-enabled asynchronously. the minimum setup time for cke (t ces ) must be satis?ed before any command other than exit is issued. 3. the address inputs (a11 - a0) depend on the command that is issued. see the idle state section of the current state truth tab le for more information. 4. the power down mode, self refresh mode, and the mode register set can only be entered from the all banks idle state. 5. must be a legal command as de?ned in the current state truth table. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 39 of 120 current state truth table (part 1 of 4) (notes: 1) current state command action notes cs ras cas we a11 a10 - a0 description idle l l l l op code mode register set set the mode register 2 l l l h x x auto or self refresh start auto or self refresh 2, 3 l l h l bs x precharge no operation l l h h bs row address bank activate activate the specified bank and row l h l l bs column write w/o precharge illegal 4 lhlhbs column read w/o precharge illegal 4 l h h l x x burst termination no operation l h h h x x no operation no operation h x x x x x device deselect no operation or power down 5 row active l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge precharge 6 l l h h bs row address bank activate illegal 4 l h l l bs column write start write; determine if auto-precharge 7, 8 lhlhbs column read start read; determine if auto-precharge 7, 8 l h h l x x burst termination no operation l h h h x x no operation no operation h x x x x x device deselect no operation read l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank activate illegal 4 l h l l bs column write terminate burst; start the write cycle 8, 9 lhlhbs column read terminate burst; start a new read cycle 8, 9 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the com- mand is being applied to. 2. both banks must be idle; otherwise it is an illegal action. 3. if cke is active (high), the sdram will start the auto (cbr) refresh operation. if cke is inactive (low), then the self refre sh mode is entered. 4. the current state only refers to one of the banks. if bs selects this bank, then the action is illegal. if bs selects the ban k not being referenced by the current state, then the action may be legal depending on the state of that bank. 5. if cke is inactive (low), then the power down mode is entered. otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satis?ed. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satis?ed. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 40 of 120 08j3348.e35853 5/98 write l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank activate illegal 4 l h l l bs column write terminate burst; start a new write cycle 8, 9 lhlhbs column read terminate burst; start the read cycle 8, 9 l h h l x x burst termination terminate the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst read with auto- precharge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 lhlhbs column read illegal 4 l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with auto- precharge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 lhlhbs column read illegal 4 l h h l x x burst termination illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst current state truth table (part 2 of 4) (notes: 1) current state command action notes cs ras cas we a11 a10 - a0 description 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the com- mand is being applied to. 2. both banks must be idle; otherwise it is an illegal action. 3. if cke is active (high), the sdram will start the auto (cbr) refresh operation. if cke is inactive (low), then the self refre sh mode is entered. 4. the current state only refers to one of the banks. if bs selects this bank, then the action is illegal. if bs selects the ban k not being referenced by the current state, then the action may be legal depending on the state of that bank. 5. if cke is inactive (low), then the power down mode is entered. otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satis?ed. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satis?ed. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 41 of 120 precharging l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge no operation; bank(s) idle after t rp l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 lhlhbs column read illegal 4 l h h l x x burst termination no operation; bank(s) idle after t rp l h h h x x no operation no operation; bank(s) idle after t rp h x x x x x device deselect no operation; bank(s) idle after t rp row activating l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4, 10 l h l l bs column write illegal 4 lhlhbs column read illegal 4 l h h l x x burst termination no operation; row active after t rcd l h h h x x no operation no operation; row active after t rcd h x x x x x device deselect no operation; row active after t rcd write recovering l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write start write; determine if auto-precharge 9 lhlhbs column read start read; determine if auto-precharge 9 l h h l x x burst termination no operation; row active after t dpl l h h h x x no operation no operation; row active after t dpl h x x x x x device deselect no operation; row active after t dpl current state truth table (part 3 of 4) (notes: 1) current state command action notes cs ras cas we a11 a10 - a0 description 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the com- mand is being applied to. 2. both banks must be idle; otherwise it is an illegal action. 3. if cke is active (high), the sdram will start the auto (cbr) refresh operation. if cke is inactive (low), then the self refre sh mode is entered. 4. the current state only refers to one of the banks. if bs selects this bank, then the action is illegal. if bs selects the ban k not being referenced by the current state, then the action may be legal depending on the state of that bank. 5. if cke is inactive (low), then the power down mode is entered. otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satis?ed. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satis?ed. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 42 of 120 08j3348.e35853 5/98 write recovering with auto- precharge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4, 9 lhlhbs column read illegal 4, 9 l h h l x x burst termination no operation; precharge after t dpl l h h h x x no operation no operation; precharge after t dpl h x x x x x device deselect no operation; precharge after t dpl refreshing l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank activate illegal l h l l bs column write illegal lhlhbs column read illegal l h h l x x burst termination no operation; idle after t rc l h h h x x no operation no operation; idle after t rc h x x x x x device deselect no operation; idle after t rc mode register accessing l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank activate illegal l h l l bs column write illegal lhlhbs column read illegal l h h l x x burst termination illegal l h h h x x no operation no operation; idle after two clock cycles h x x x x x device deselect no operation; idle after two clock cycles current state truth table (part 4 of 4) (notes: 1) current state command action notes cs ras cas we a11 a10 - a0 description 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of the bank that the com- mand is being applied to. 2. both banks must be idle; otherwise it is an illegal action. 3. if cke is active (high), the sdram will start the auto (cbr) refresh operation. if cke is inactive (low), then the self refre sh mode is entered. 4. the current state only refers to one of the banks. if bs selects this bank, then the action is illegal. if bs selects the ban k not being referenced by the current state, then the action may be legal depending on the state of that bank. 5. if cke is inactive (low), then the power down mode is entered. otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satis?ed. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satis?ed. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 43 of 120 absolute maximum ratings symbol parameter rating units notes vdd power supply voltage -1.0 to +4.6 v 1 vddq power supply voltage for output -1.0 to +4.6 v 1 v in input voltage -1.0 to +4.6 v 1 v out output voltage -1.0 to +4.6 v 1 t a operating temperature (ambient) 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation 1.0 w 1 i out short circuit output current 50 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. recommended dc operating conditions (t a = 0 to 70?c) symbol parameter rating units notes min. typ. max. vdd supply voltage 3.0 3.3 3.6 v 1 vddq supply voltage for output 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 vdd + 0.3 v 1 v il input low voltage -0.3 0.8 v 1 1. all voltages referenced to v ss and vssq. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 44 of 120 08j3348.e35853 5/98 capacitance (t a = 25 c, f=1mhz, v dd = 3.3v 0.3v) symbol parameter min. typ max. units notes c i1 input capacitance (a0 - a11) 2.0 2.7 4.0 pf 1 c i2 input capacitance ( ras, cas, we, cs, clk, cke, dqm) 2.0 2.7 4.0 pf 1 c o output capacitance (dq0 - dq15) 2.0 4.0 5.0 pf 1 1. multiply given planar values by 2 for 2-high stacked device. dc electrical characteristics (t a = 0 to +70?c, v dd = 3.3v 0.3v) symbol parameter min. max. units i i(l) input leakage current, any input (0.0v v in 3.6v), all other pins not under test = 0v -1 +1 m a i o(l) output leakage current (d out is disabled, 0.0v v out 3.6v) -1 +1 m a v oh output level (ttl) output h level voltage (i out = -2.0ma) 2.4 vddq v v ol output level (ttl) output l level voltage (i out = +2.0ma) 0.0 0.4 v discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 45 of 120 standby and refresh currents (t a = 0 to +70?c, v dd = 3.3v 0.3v) (notes: 1) parameter symbol test condition organization units notes x4 x8 x16 precharge standby current in power down mode i cc1 p cke v il (max), t ck = 15ns 333ma 2 i cc1 ps cke v il (max), t ck = infinity 222ma precharge standby current in non-power down mode i cc1 n cke 3 v ih (min), t ck = 15ns input change every 30ns 25 25 25 ma cs=high 2 i cc1 ns cke 3 v ih (min), t ck = infinity no input change 10 10 10 ma 2 active standby current in power down mode i cc2 p cke v il (max), t ck = 15ns 3 3 3 ma 3, 11 i cc2 ps cke v il (max), t ck = infinity 2 2 2 ma 4, 11 active standby current in non-power down mode i cc2 n cke 3 v ih (min), t ck = 15ns input change every 30ns 25 25 25 ma cs=high 5 i cc2 ns cke 3 v ih (min), t ck = infinity no input change 15 15 15 ma 6, 11 auto (cbr) refresh current i cc3 cas latency = 1 t rc 3 t rc (min) -10 85 85 85 ma 7, 8, 9, 10 cas latency = 2 t rc 3 t rc (min) -80 110 110 110 -360 90 ma -10 90 90 90 cas latency = 3 t rc 3 t rc (min) -80 140 140 140 -360 140 ma -10 110 110 110 self refresh current i cc4 cke 0.2v -80/-10 2 2 2 ma 2 -360 2 ma 1. for stacked devices: only one deck may be active at a time, except during self refresh. 2. for stacked devices: multiply the given planar (individual deck) values by 2. 3. for stacked devices: this is the active portion only.the total stack current includes the precharge standby current of the ina ctive deck (i cc2 p + i cc1 p). 4. for stacked devices: this is the active portion only.the total stack current includes the precharge standby current of the ina ctive deck (i cc2 ps + i cc1 ps). 5. for stacked devices: this is the active portion only.the total stack current includes the precharge standby current of the ina ctive deck (i cc2 n + i cc1 n). 6. for stacked devices: this is the active portion only.the total stack current includes the precharge standby current of the ina ctive deck (i cc2 ns+ i cc1 ns). 7. for stacked devices: this is the active portion only.the total stack current includes the precharge standby current of the ina ctive deck (i cc3 +i cc1 n). 8. the speci?ed values are valid when addresses are changed no more than once during t ck (min). 9. the specified values are valid when no operation commands are registered on every rising clock edge during t rc (min). 10. the specified values are valid when data inputs (dqs) are stable during t rc (min). 11. active standby current will be higher if clock suspend is entered during a burst read cycle (add 1ma per dq). discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 46 of 120 08j3348.e35853 5/98 operating currents (t a = 0 to +70?c, v dd = 3.3v 0.3v) symbol parameter test condition cas latency t rc (min) speed sort organization units notes x4 x8 x16 i cc5 operating current burst length = 1 t rc = t rc (min) t ck 3 t ck (min) i o = 0ma cl=1 90 ns -10 95 95 95 ma 1, 2, 3 cl=2 72 ns -80 130 130 135 ma 90 ns -360 105 90 ns -10 105 105 110 cl=3 72 ns -80 155 155 160 ma 70 ns -360 160 90 ns -10 125 125 130 i cc6 operating current burst length = 2 t rc = t rc (min) t ck 3 t ck (min) i o = 0ma cl=1 120 ns -10 75 75 80 ma 1, 2, 3, 4 cl=2 84 ns -80 125 125 130 ma 105 ns -360 100 105 ns -10 100 100 105 cl=3 80 ns -80 155 155 160 ma 80 ns -360 155 100 ns -10 125 125 130 i cc7 operating current burst length = 4 t rc = t rc (min) t ck 3 t ck (min) i o = 0ma cl=1 180 ns -10 65 65 70 ma 1, 2, 3, 4 cl=2 108 ns -80 115 120 125 ma 135 ns -360 95 135 ns -10 90 95 100 cl=3 96 ns -80 150 155 160 ma 100 ns -360 150 120 ns -10 120 125 130 i cc8 operating current burst length = 8 t rc = t rc (min) t ck 3 t ck (min) i o = 0ma cl=1 300 ns -10 55 60 65 ma 1, 2, 3, 4 cl=2 156 ns -80 105 110 120 ma 195 ns -360 90 195 ns -10 85 90 100 cl=3 128 ns -80 150 155 165 ma 140 ns -360 145 160 ns -10 120 125 135 1. the specified values are obtained with the output open. 2. the specified values are valid when addresses and dqs are changed no more than once during t ck (min). 3. for stacked devices: this is the active portion only.the total stack current includes the precharge standby current of the in active deck (operating current+ i cc1 n). 4. the specified values are obtained when the programmed burst length is executed to completion without interruption by a subse- quent burst read or write cycle. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 47 of 120 i cc9 operating current burst length = full page t rc = infinity t ck 3 t ck (min) i o = 0ma cl=1 t rc = t ck =30 ns -10 40 45 55 ma 1, 2, 3, 4 cl=2 t rc = t ck =12 ns -80 90 95 110 ma t rc = t ck =15 ns -360 75 t rc = t ck =15 ns -10 70 75 90 cl=3 t rc = t ck =8 ns -80 125 130 170 ma t rc = t ck =10 ns -360 105 t rc = t ck =10 ns -10 100 105 135 i cc10 operating current 1-n rule (continuous read/write cycles with new column address registered each clock cycle) t rc = infinity t ck 3 t ck (min) i o = 0ma cl=1 t rc = t ck =30 ns -10 85 85 90 ma 1, 2, 3 cl=2 t rc = t ck =12ns -80 165 165 175 ma t rc = t ck =15 ns -360 130 t rc = t ck =15 ns -10 130 130 140 cl=3 t rc = t ck =8 ns -80 220 220 240 ma t rc = t ck =10 ns -360 175 t rc = t ck =10 ns -10 175 175 190 operating currents (t a = 0 to +70?c, v dd = 3.3v 0.3v) symbol parameter test condition cas latency t rc (min) speed sort organization units notes x4 x8 x16 1. the specified values are obtained with the output open. 2. the specified values are valid when addresses and dqs are changed no more than once during t ck (min). 3. for stacked devices: this is the active portion only.the total stack current includes the precharge standby current of the in active deck (operating current+ i cc1 n). 4. the specified values are obtained when the programmed burst length is executed to completion without interruption by a subse- quent burst read or write cycle. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 48 of 120 08j3348.e35853 5/98 ac characteristics (t a = 0 to +70?c, v dd = 3.3v 0.3v) 1. an initial pause of 100 m s is required after power-up, then a precharge all banks command must be given followed by a minimum of two auto (cbr) refresh cycles before the mode register set operation can begin. 2. the transition time is measured between v ih and v il (or between v il and v ih ). 3. in addition to meeting the transition rate speci?cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.40v crossover point. 5. ac measurements assume t t =1.0 ns. clock and clock enable parameters symbol parameter -80 -360 -10 units notes min. max. min. max. min. max. t ck3 clock cycle time, cas latency=3 8 125mhz 10 100mhz 10 100mhz ns t ck2 clock cycle time, cas latency=2 12 83mhz 15 66mhz 15 66mhz ns t ck1 clock cycle time, cas latency=1 30 33mhz ns t ac3 clock access time, cas latency=3 6 5.5 8 ns 1, 2 t ac2 clock access time, cas latency=2 7 9 9 ns 1, 2 t ac1 clock access time, cas latency=1 27 ns 1, 2 t ckh clock high pulse width 3 3 3.5 ns 3 t ckl clock low pulse width 3 3 3.5 ns 3 t ces clock enable set-up time 2 2 3 ns t ceh clock enable hold time 1 1 1 ns t cesp cke set-up time (power down mode) 2 2 3 ns t t transition time (rise and fall) 1 30 1 30 1 30 ns 1. access time is measured at 1.4v. see ac characteristics: notes 1,2,3,4,5 and load circuit. 2. access time is measured assuming a clock rise time of 1 ns. if clock rise time is longer than 1 ns, then (trise/2-0.5)ns shou ld be added to the parameter. 3. assumes clock rise and fall times are equal to 1 ns. if rise or fall time exceeds 1 ns, then other ac parameters under consid er- ation should be compensated by an additional [(trise+tfall)/2-1]ns. output input clock t oh t setup t hold t ac t lz v il 1.4v v ih t t vtt=1.4v output 50 w 50pf z o = 50 w ac output load circuit 1.4v 1.4v discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 49 of 120 common parameters symbol parameter -80 -360 -10 units min. max. min. max. min. max. t cs command setup time 2 23ns t ch command hold time 1 11ns t as address and bank select set-up time 2 23ns t ah address and bank select hold time 1 11ns t rcd ras to cas delay 24 20 30 ns t rc bank cycle time 72 120k 70 120k 90 120k ns t ras active command period 48 120k 50 120k 60 120k ns t rp precharge time 24 20 30 ns t rrd bank to bank delay time 16 20 20 ns t ccd cas to cas delay time (same bank) 1 11 clk refresh cycle symbol parameter -80 -360 -10 units notes min. max. min. max. min. max. t ref refresh period 64 64 64 ms 1, 2 t srex self refresh exit time 10ns + t rc 10ns + t rc 10ns + t rc ns3 1. 4096 cycles. 2. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake- up the device. 3. self refresh exit is an asynchronous operation. self refresh exit is accomplished by starting the clock (clk) and then assert ing cke high. during the exit time (t srex ), no commands may be issued until t rc is satis?ed and cke must remain high. it is recom- mended to hold cs high during the self refresh exit time, but nop commands may be issued with each rising clock edge during this period as an alternative. to prevent erroneous exit of self refresh operation, a glitch suppressor circuit is incorporated into the cke receiver. if cke is asserted high (system noise) for less than 10ns (approximately), then the device will not exit self refresh opera- tion. read cycle symbol parameter -80 -360 -10 units notes min. max. min. max. min. max. t oh data out hold time 2.5 3 3 ns 1 t lz data out to low impedance time 2.5 2.5 3 ns t hz3 data out to high impedance time,cl= 3 2.5 6 2.5 5.5 3 8 ns 2 t hz2 data out to high impedance time,cl= 2 2.5 7 2.5 8 3 8 ns 2 t hz1 data out to high impedance time,cl= 1 3 15ns2 t dqz dqm data out disable latency 2 2 2 clk 1. -360: 50pf load. 2. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 50 of 120 08j3348.e35853 5/98 write cycle symbol parameter -80 -360 -10 units notes min. max. min. max. min. max. t ds data in set-up time 2 2 3 ns t dh data in hold time 1 1 1 ns t dpl data input to precharge 8 15 10 ns t dqw dqm write mask latency 0 0 0 clk discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 51 of 120 clock frequency and latency symbol parameter -80 -360 -10 units fck clock frequency 125 83 100 66 100 66 33 mhz t ck clock cycle time 8 12 10 15 10 15 30 ns t aa cas latency 3232321clk t rcd ras to cas delay 3222321clk t rl ras latency 6454642clk t rc bank cycle time 9676963clk t ras minimum bank active time 6454642clk t rp precharge time 3222321clk t dpl data in to precharge 1121111clk t dal data in to active/refresh 4343432clk t rrd bank to bank delay time 2222221clk t ccd cas to cas delay time 1111111clk t wl write latency 0000000clk t dqw dqm write mask latency 0000000clk t dqz dqm data disable latency 2222222clk t csl clock suspend latency 1111111clk discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 52 of 120 08j3348.e35853 5/98 timing diagrams page ac parameters for write timing ................................................................................................. .............. 55 ac parameters for read timing.................................................................................................. ............. 56 mode register set .............................................................................................................. ...................... 57 power on sequence and auto refresh (cbr)....................................................................................... ... 58 clock suspension during a burst read (using cke) cas latency = 1 ............................................................................................................... 5 9 cas latency = 2 ............................................................................................................... 6 0 cas latency = 3, t rcd = 3................................................................................................ 61 clock suspension during a burst write (using cke) cas latency = 1 ............................................................................................................... 6 2 cas latency = 2 ............................................................................................................... 6 3 cas latency = 3, t rcd = 3................................................................................................ 64 power down mode and clock suspend .............................................................................................. ..... 65 auto refresh (cbr) ............................................................................................................. ..................... 66 self refresh (entry and exit) .................................................................................................. .................. 67 random column read (page within same bank) cas latency = 1 ............................................................................................................... 6 8 cas latency = 2 ............................................................................................................... 6 9 cas latency = 3, t rcd , t rp = 3......................................................................................... 70 cas latency = 3, t rcd , t rp = 2......................................................................................... 71 random column write (page within same bank) cas latency = 1 ............................................................................................................... 7 2 cas latency = 2 ............................................................................................................... 7 3 cas latency = 3, t rcd , t rp = 3, t dpl = 1 ......................................................................... 74 cas latency = 3, t rcd , t rp = 2, t dpl = 2 .......................................................................... 75 random row read (interleaving banks) cas latency = 1 ............................................................................................................... 7 6 cas latency = 2 ............................................................................................................... 7 7 cas latency = 3, t rcd , t rp = 3......................................................................................... 78 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 53 of 120 timing diagrams page random row write (interleaving banks) cas latency = 1............................................................................................................... 7 9 cas latency = 2............................................................................................................... 8 0 cas latency = 3, t rcd , t rp = 3 ........................................................................................ 81 read and write cycle cas latency = 1............................................................................................................... 8 2 cas latency = 2............................................................................................................... 8 3 cas latency = 3, t rcd , t rp = 3 ........................................................................................ 84 interleaved column read cycle cas latency = 1............................................................................................................... 8 5 cas latency = 2............................................................................................................... 8 6 cas latency = 3, t rcd , t rp = 3 ........................................................................................ 87 interleaved column write cycle cas latency = 1............................................................................................................... 8 8 cas latency = 2............................................................................................................... 8 9 cas latency = 3, t rcd , t rp = 3, t dpl = 1.......................................................................... 90 cas latency = 3, t rcd , t rp = 2, t dpl = 2.......................................................................... 91 auto-precharge after a read burst cas latency = 1............................................................................................................... 9 2 cas latency = 2............................................................................................................... 9 3 cas latency = 3, t rcd , t rp = 3 ........................................................................................ 94 auto-precharge after a write burst cas latency = 1............................................................................................................... 9 5 cas latency = 2............................................................................................................... 9 6 cas latency = 3, t rcd , t rp = 3 ........................................................................................ 97 full page read cycle cas latency = 1............................................................................................................... 9 8 cas latency = 2............................................................................................................... 9 9 cas latency = 3, t rcd , t rp = 3 ........................................................................................ 100 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 54 of 120 08j3348.e35853 5/98 timing diagrams page full page write cycle cas latency = 1 ............................................................................................................... 1 01 cas latency = 2 ............................................................................................................... 1 02 cas latency = 3, t rcd , t rp = 3......................................................................................... 103 byte write operation........................................................................................................... ...................... 104 burst read and single write operation.......................................................................................... .......... 105 full page burst read and single write operation................................................................................ .... 106 random row read (interleaving banks)........................................................................................... ....... 107 full page random column read ................................................................................................... .......... 108 full page random column write .................................................................................................. ........... 109 precharge termination of a burst cas latency = 1 ............................................................................................................... 1 10 cas latency = 2 ............................................................................................................... 1 11 cas latency = 3, t rcd , t rp = 3......................................................................................... 112 cs function (only cs signal needs to be asserted at minimum rate)...................................................... 113 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 55 of 120 \ clk cke cs dq ras cas we a11(bs) dqm ac parameters for write timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 t ces t cs t ch t ceh t as t rcd t rc t dal t rp t ds activate command bank a write with auto-precharge command bank a activate command bank b write with auto-precharge command bank b activate command bank a write command bank a precharge command bank a activate command bank a t dh ax0 ax3 ax2 ax1 bx0 bx3 bx2 bx1 ay0 ay3 ay2 ay1 t ck2 t ckh t ckl begin auto-precharge bank a begin auto-precharge bank b t dpl t rrd activate command bank b ray cbx cay ray rbx rbx cax rby rby raz raz rax rax t ah discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 56 of 120 08j3348.e35853 5/98 \(read timing) clk cke cs dq ras cas we a11(bs) dqm ac parameters for read timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 burst length = 2, cas latency = 2 a0 - a9 t cs t ch t ceh t as t ah t rrd t rcd t ras t lz activate command bank a activate command bank b activate command bank a precharge command bank a t ces t ck2 read command bank a read with auto-precharge command bank b t rc t rp t ac2 t oh t hz t ckh bx0 begin auto- precharge bank b bx1 t hz cbx ray rbx rbx ray cax rax rax t ckl ax0 ax1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 57 of 120 \ clk cke cs dq ras cas we a11(bs) dqm mode register set t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 cas latency = 2 a0 - a9 precharge command all banks mode register set command any command address key 2 clock min. t rp t ck2 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 58 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm power on sequence and auto refresh (cbr) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 precharge command all banks t rp minimum of 2 refresh cycles are required 1st auto refresh command t rc high level is required 2nd auto refresh command inputs must be stable for 100 m s t ck2 any command 2 clock min. mode register address key set command discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 59 of 120 \ clk cke cs dq ras cas we a11(bs) dqm clock suspension during burst read (using cke) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 cax rax ax0 ax1 ax2 ax3 activate command bank a read command bank a clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax t hz t ck1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 60 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm clock suspension during burst read (using cke) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 cax rax ax0 ax1 ax2 ax3 activate command bank a clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax read command bank a t hz t ck2 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 61 of 120 \ clk cke cs dq ras cas we a11(bs) dqm clock suspension during burst read (using cke) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd = 3 a0 - a9 rax ax0 ax1 ax2 ax3 activate command bank a clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax read command bank a cax t hz t ck3 read command may be issued 1 clock sooner for -360 (t rcd = 2 clocks) discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 62 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm clock suspension during burst write (using cke) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 cax rax activate command bank a write command bank a clock suspend 1 cycle clock suspend 2 cycles clock suspend 3 cycles dax3 dax2 dax0 dax1 rax t ck1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 63 of 120 \ clk cke cs dq ras cas we a11(bs) dqm clock suspension during burst write (using cke) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 cax rax activate command bank a rax dax0 clock suspend 1 cycle dax1 dax2 dax3 clock suspend 2 cycles clock suspend 3 cycles write command bank a t ck2 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 64 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm clock suspension during burst write (using cke) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd = 3 a0 - a9 rax activate command bank a rax cax dax0 clock suspend 1 cycle dax1 dax2 dax3 clock suspend 2 cycles clock suspend 3 cycles write command bank a t ck3 write command may be issued 1 clock sooner for -360 (t rcd = 2 clocks) discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 65 of 120 \ clk cke cs dq ras cas we a11(bs) dqm power down mode and clock suspend t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 t cesp t cesp valid cax rax rax ax2 ax0 ax1 ax3 activate command bank a clock suspension mode entry clock suspension mode exit read command bank a active standby clock suspension start clock suspension end precharge command bank a power down mode entry precharge standby power down mode exit t hz any command t ck2 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 66 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm auto refresh (cbr) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 ax0 ax1 burst length = 4, cas latency = 2 activate command read command precharge command auto refresh command auto refresh command t rc t rp t rc t ck2 all banks cax rax rax bank a bank a ax2 ax3 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 67 of 120 \ clk cke cs dq ras cas we a11(bs) dqm self refresh (entry and exit) ***note: the clk signal must be reestablished prior to cke returning high. t2 t3 t4 t0 t1 hi-z a10 all banks must be idle self refresh entry begin self refresh exit t srex self refresh self refresh exit t rc a0 - a9 exit command tm tm+2 tm+3 tm+4 tm+5 tm+1 tm+7 tm+8 tm+9 tm+10 tm+6 tm+13 tm+11 tm+12 tm+15 tm+14 any command discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 68 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm random column read (page within same bank) (1 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 activate command bank a precharge command bank a caw raw raw cax read command bank a cay read command bank a activate command bank a raz caz read command bank a read command bank a raz aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az0 az1 az2 az3 ay2 ay3 t ck1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 69 of 120 \ clk cke cs dq ras cas we a11(bs) dqm random column read (page within same bank) (2 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az0 az1 az2 az3 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck2 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 70 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm random column read (page within same bank) (3 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd ,t rp = 3 a0 - a9 activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck3 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 71 of 120 \ clk cke cs dq ras cas we a11(bs) dqm random column read (page within same bank) (4 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd ,t rp = 2 a0 - a9 activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck3 az0 az1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 72 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm random column write (page within same bank) (1 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 rbw rbw cbw cbx activate command bank b write command bank b write command bank b cby write command bank b rbz rbz precharge command bank b activate command bank b cbz write command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz3 dbz2 dbz1 t ck1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 73 of 120 \ clk cke cs dq ras cas we a11(bs) dqm random column write (page within same bank) (2 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz3 dbz2 dbz1 t ck2 activate command bank b cax write command bank b raw raw activate command bank b cbz write command bank b rbz rbz activate command bank b cbw write command bank b rbw rbw discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 74 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm random column write (page within same bank) (3 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd ,t rp = 3, t dpl = 1 a0 - a9 cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz1 t ck3 activate command bank b cbz write command bank b rbz rbz activate command bank b cbw write command bank b rbw rbw dbz2 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 75 of 120 \ clk cke cs dq ras cas we a11(bs) dqm random column write (page within same bank) (4 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd ,t rp = 2, t dpl = 2 a0 - a9 cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz1 t ck3 activate command bank b cbz write command bank b rbz rbz activate command bank b cbw write command bank b rbw rbw dbz2 dbz3 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 76 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm random row read (interleaving banks) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 1 a0 - a9 activate command bank b cbx rbx rbx cby read command bank b read command bank a read command bank b bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 by0 by1 by2 t ck1 high t rcd t ac1 t rp cax rax rax rby rby activate command bank a precharge command bank b activate command bank b precharge command bank a ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 77 of 120 \ clk cke cs dq ras cas we a11(bs) dqm random row read (interleaving banks) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 2 a0 - a9 cby read command bank b read command bank a bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 by0 by1 t ck2 high t rcd t ac2 t rp cax precharge command bank b ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 78 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm random row read (interleaving banks) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 3, t rcd ,t rp = 3 a0 - a9 cby read command bank b by0 t ck3 high t ac3 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby t rcd precharge command bank b cax read command bank a t rp bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 precharge command bank a discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 79 of 120 \ clk cke cs dq ras cas we a11(bs) dqm random row write (interleaving banks) (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 1 a0 - a9 t ck1 high cax rax rax write command bank a t rcd activate command bank a cbx rbx rbx write command bank b activate command bank b ray ray precharge command bank a activate command bank a t rp precharge command bank b write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t dpl discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 80 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm random row write (interleaving banks) (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 2 a0 - a9 t ck2 high t rcd t rp write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t dpl write command bank a cax activate command bank a rax rax activate command bank b rbx rbx cbx precharge command bank a write command bank b activate command bank a ray ray cay precharge command bank b write command bank a day4 t dpl discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 81 of 120 \ clk cke cs dq ras cas we a11(bs) dqm random row write (interleaving banks) (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 8, cas latency = 3, t rcd ,t rp = 3 a0 - a9 t ck3 high dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day2 day1 day0 write command bank a cax activate command bank a rax rax activate command bank b rbx rbx activate command bank a ray ray day3 t dpl cbx write command bank b precharge command bank a write command bank a cay precharge command bank b t rp t dpl t rcd discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 82 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm read and write cycle (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 t ck1 rax rax cax read command bank a activate command bank a write command bank a cay caz read command bank a az0 day0 az1 az3 day1 day3 ax0 ax1 ax3 ax2 the write data is masked with a zero clock latency the read data is masked with a two clock latency discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 83 of 120 \ clk cke cs dq ras cas we a11(bs) dqm read and write cycle (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 t ck2 write command bank a cay caz read command bank a az0 day0 az1 az3 day1 day3 ax0 ax1 ax3 ax2 the write data is masked with a zero clock latency the read data is masked with a two clock latency activate command bank a rax rax cax read command bank a discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 84 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm read and write cycle (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd, t rp = 3 a0 - a9 t ck3 write command bank a cay caz read command bank a az0 day0 az1 az3 day1 day3 ax0 ax1 ax3 ax2 the write data is masked with a zero clock latency the read data is masked with a two clock latency activate command bank a rax rax cax read command bank a discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 85 of 120 \ clk cke cs dq ras cas we a11(bs) dqm interleaved column read cycle (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 t ck1 rax rax cax read command bank a activate command bank a t rcd t ac1 rbw rbw cbw read command bank b activate command bank b cbx read command bank b cby read command bank b cbz read command bank b cay read command bank a precharge command bank a precharge command bank b ax0 ax3 ax2 ax1 bw0 bx1 bx0 bw1 by0 ay1 ay0 by1 bz0 bz3 bz2 bz1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 86 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm interleaved column read cycle (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 t ck2 t rcd t ac2 cbx read command bank b cby read command bank b cay read command bank a precharge command bank b ax0 ax3 ax2 ax1 bw0 bx1 bx0 bw1 by0 ay1 ay0 by1 bz0 bz3 bz2 bz1 activate command bank a rax rax cax read command bank a cbw read command bank b activate command bank b rbw rbw cbz precharge command bank a read command bank b discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 87 of 120 \ clk cke cs dq ras cas we a11(bs) dqm interleaved column read cycle (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd, t rp = 3 a0 - a9 t ck3 t rcd t ac3 cby read command bank b cbz read command bank b cay read command bank a precharge command bank b ax0 ax3 ax2 ax1 bx0 by1 by0 bx1 bz0 bz1 ay0 ay3 ay2 ay1 activate command bank a rax rax cbx read command bank b cax activate command bank b read command bank a rbx rbx precharge command bank a discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 88 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm interleaved column write cycle (1 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 t ck1 rbw rax rbw cax rax activate command bank a activate command bank b write command bank a cbw write command bank b cbz write command bank b cby write command bank b cbx write command bank b write command bank a cay precharge command bank a precharge command bank b dax3 dax2 dax1 dax0 dbx1 dbx0 dbw1 dbw0 day1 day0 dby1 dby0 dbz3 dbz2 dbz1 dbz0 t rrd t rcd t rp t dpl t rp discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 89 of 120 \ clk cke cs dq ras cas we a11(bs) dqm interleaved column write cycle (2 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 t ck2 cbw write command bank b cbz write command bank b cby write command bank b cbx write command bank b write command bank a cay precharge command bank a precharge command bank b dax3 dax2 dax1 dax0 dbx1 dbx0 dbw1 dbw0 day1 day0 dby1 dby0 dbz3 dbz2 dbz1 dbz0 t rrd t rcd t dpl activate command bank a rax rax write command bank a cax activate command bank b rbw rbw t rp t rp discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 90 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm interleaved column write cycle (3 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd ,t rp = 3, t dpl = 1 a0 - a9 t ck3 cbw write command bank b cby write command bank b cbx write command bank b write command bank a cay precharge command bank b dax3 dax2 dax1 dax0 dbx1 dbx0 dbw1 dbw0 day1 day0 dby1 dby0 dbz3 dbz2 dbz1 dbz0 t rrd t rcd t dpl activate command bank a rax rax write command bank a cax activate command bank b rbw rbw t rp cbz write command bank b precharge command bank a discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 91 of 120 \ clk cke cs dq ras cas we a11(bs) dqm interleaved column write cycle (4 of 4) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd ,t rp = 2, t dpl = 2 a0 - a9 t ck3 cbw write command bank b cby write command bank b cbx write command bank b write command bank a cay precharge command bank b dax3 dax2 dax1 dax0 dbx1 dbx0 dbw1 dbw0 day1 day0 dby1 dby0 dbz3 dbz2 dbz1 dbz0 t rrd t rcd activate command bank a rax rax write command bank a cax activate command bank b rbw rbw t dpl cbz write command bank b precharge command bank a t rp discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 92 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm auto-precharge after read burst (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 t ck1 high rax rax cax read command bank a activate command bank a rbz rbz cbz activate command bank b read with auto-precharge command bank b rbx rbx cbx activate command bank b read with auto-precharge command bank b rby cay rby activate command bank b read with auto-precharge command bank a read with auto-precharge command bank b cby start auto-precharge bank b start auto-precharge bank a start auto-precharge bank b ax3 ax2 ax0 ax1 bx3 bx2 bx0 bx1 ay3 ay2 ay0 ay1 by3 by2 by0 by1 bz3 bz2 bz0 bz1 start auto-precharge bank b discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 93 of 120 \ clk cke cs dq ras cas we a11(bs) dqm auto-precharge after read burst (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 t ck2 high read with auto-precharge command bank b cby start auto-precharge bank b start auto-precharge bank a start auto-precharge bank b ax3 ax2 ax0 ax1 bx3 bx2 bx0 bx1 ay3 ay2 ay0 ay1 by3 by2 by0 by1 az2 az0 az1 activate command bank a rax rax cax read command bank a activate command bank b rbx rbx read with auto-precharge command bank b cbx read with auto-precharge command bank a cay activate command bank b rby rby activate command bank a raz raz read with auto-precharge command bank a caz start auto-precharge bank a discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 94 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm auto-precharge after read burst (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd ,t rp = 3 a0 - a9 t ck3 high read with auto-precharge command bank b cby start auto-precharge bank b start auto-precharge bank a ax3 ax2 ax0 ax1 bx3 bx2 bx0 bx1 ay3 ay2 ay0 ay1 activate command bank a rax rax read with auto-precharge command bank b cbx read with auto-precharge command bank a activate command bank b rbx cax rbx activate command bank b read command bank a rby cay rby start auto-precharge bank b by3 by2 by0 by1 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 95 of 120 \ clk cke cs dq ras cas we a11(bs) dqm auto-precharge after write burst (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 1 a0 - a9 t ck1 high rax rax cax write command bank a activate command bank a raz raz caz activate command bank a write with auto-precharge command bank a rby cay rby activate command bank b write with auto-precharge command bank a write with auto-precharge command bank b cby start auto-precharge bank b start auto-precharge bank a start auto-precharge bank b activate command bank b rbx rbx write with auto-precharge command bank b cbx dax3 dax2 dax1 dax0 dbx3 dbx2 dbx1 dbx0 day3 day2 day1 day0 dby3 dby2 dby1 dby0 daz3 daz2 daz1 daz0 start auto- precharge bank a discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 96 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm auto-precharge after write burst (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 t ck2 high write with auto-precharge command bank b cby start auto-precharge bank b start auto-precharge bank a start auto-precharge bank b activate command bank b rbx rbx write with auto-precharge command bank b cbx dax3 dax2 dax1 dax0 dbx3 dbx2 dbx1 dbx0 day3 day2 day1 day0 dby3 dby2 dby1 dby0 daz3 daz2 daz1 daz0 activate command bank a raz raz write command bank a cax write with auto-precharge command bank a cay activate command bank b rby rby activate command bank a rax rax write with auto-precharge command bank a caz start auto precharge bank a discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 97 of 120 \ clk cke cs dq ras cas we a11(bs) dqm auto-precharge after write burst (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 3, t rcd ,t rp = 3 a0 - a9 t ck3 high start auto-precharge bank b start auto-precharge bank a write with auto-precharge command bank b cbx dax3 dax2 dax1 dax0 dbx3 dbx2 dbx1 dbx0 day3 day2 day1 day0 dby3 dby2 dby1 dby0 write command bank a write with auto-precharge command bank a cay activate command bank b rby rby activate command bank a rax rax rbx cax rbx activate command bank b write with auto-precharge command bank b cby start auto- bank b precharge discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 98 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm full page read cycle (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 1 a0 - a9 t ck1 rbx rax rbx cax rax high read command bank a activate command bank a activate command bank b ax ax+1 ax-1 ax-2 ax+2 ax bx bx+1 bx+5 bx+4 bx+3 bx+2 bx+7 bx+6 cbx read command bank b rby rby precharge command bank b activate command bank b burst stop command full page burst operation does not terminate when the burst length is satisfied; ax+1 t rp page length: 2mb x 4i/o x 2 banks = 1024 1mb x 8i/o x 2 banks = 512 512kb x 16i/o x 2 banks = 256 t rrd the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. bursting beginning with the starting address. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 99 of 120 \ clk cke cs dq ras cas we a11(bs) dqm full page read cycle (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 2 a0 - a9 t ck2 high ax ax+1 ax-1 ax-2 ax+2 ax bx bx+1 bx+5 bx+4 bx+3 bx+2 ax+1 bx+6 cbx read command bank b precharge command bank b burst stop command cax read command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby t rp full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. bursting beginning with the starting address. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 100 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm full page read cycle (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 3, t rcd, t rp = 3 a0 - a9 t ck3 high ax ax+1 ax-1 ax-2 ax+2 ax bx bx+1 bx+5 bx+4 bx+3 bx+2 ax+1 cbx read command bank b precharge command bank b burst stop command cax read command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby full page burst operation does not the burst counter wraps from the highest order page address back to zero during this time interval. terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address. t rp discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 101 of 120 \ clk cke cs dq ras cas we a11(bs) dqm full page write cycle (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 1 a0 - a9 t ck1 rbx rax rbx cax rax high write command bank a activate command bank a activate command bank b dax dax+1 dax-1 dax+2 dax+2 dax dbx dbx+1 cbx write command bank b rby rby precharge command bank b activate command bank b burst stop command dax+1 page length: 2mb x 4i/o x 2 banks = 1024 1mb x 8i/o x 2 banks = 512 512kb x 16i/o x 2 banks = 256 data is ignored. dbx+3 dbx+2 dbx+4 dbx+5 dbx+6 dbx+7 full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. bursting beginning with the starting address. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 102 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm full page write cycle (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 2 a0 - a9 t ck2 high cbx write command bank b precharge command bank b burst stop command cax write command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby data is ignored. dax dax+1 dax-1 dax+3 dax+2 dax dbx dbx+1 dax+1 dbx+3 dbx+2 dbx+4 dbx+5 dbx+6 full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. bursting beginning with the starting address. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 103 of 120 \ clk cke cs dq ras cas we a11(bs) dqm full page write cycle (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 3, t rcd, t rp = 3 a0 - a9 t ck3 high cbx write command bank b precharge command bank b burst stop command cax write command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby dax dax+1 dax-1 dax+3 dax+2 dax dbx dbx+1 dax+1 dbx+3 dbx+2 dbx+4 dbx+5 full page burst operation does not the burst counter wraps from the highest order page address back to zero during this time interval. terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address. data is ignored. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 104 of 120 08j3348.e35853 5/98 \ clk cke cs dq 0 - dq 7 ras cas we a11(bs) ldqm byte write operation t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4, cas latency = 2 a0 - a9 t ck2 activate command bank a rax rax cax read command bank a write command bank a cay high caz read command bank a dq 8 - dq 15 hi-z udqm ax3 day1 day3 ax2 ax1 az1 az2 day0 ax0 az3 lower byte is masked upper byte is masked upper byte is masked lower byte is masked lower byte is masked ax0 day1 day2 ax2 ax1 az1 az2 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 105 of 120 \ clk cke cs dq 0 - dq 7 ras cas we a11(bs) ldqm a10 a0 - a9 d q 8 - dq 15 udqm burst read and single write operation t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z burst length = 4, cas latency = 2 t ck2 activate command bank a rav rav cav read command bank a single write command bank a caw high cay read command bank a av0 daw0 hi-z av2 av1 av3 dax0 av2 av1 ay2 daw0 ay0 ay3 av0 av3 single write command bank a ay3 single write command bank a az0 az0 cax caz lower byte is masked ay0 ay1 upper byte is masked lower byte is masked discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 106 of 120 08j3348.e35853 5/98 \ clk cke cs dq 0 - dq 7 ras cas we a11(bs) ldqm a10 a0 - a9 d q 8 - dq 15 udqm full page burst read and single write operation t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z burst length = full page, cas latency = 3, t rcd, t rp = 3 t ck3 activate command bank a rav rav cav read command bank a single write command bank a caw high cay read command bank a av0 daw0 hi-z av2 av1 av3 dax0 av2 av1 ay2 daw0 ay0 ay3 av0 av3 single write command bank a ay3 cax ay0 ay1 dax0 ay2 ay1 burst stop command burst stop command discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 107 of 120 \ clk cke cs dq ras cas we a11(bs) dqm random row read (interleaving banks) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 2, cas latency = 1 a0 - a9 t ck1 rbu rby rax rbx raw rbw rav rbv rau ray rbz raz rbu rby rax rbx raw rbw rav rbv rau ray rbz raz cax cbx caw cbw cav cbv cau cbu cby cay cbz bu0 au1 au0 bu1 bv0 av1 av0 bv1 bw0 aw1 aw0 bw1 bx0 ax1 ax0 bx1 by0 ay1 ay0 by1 bz0 high t rp t rp t rp t rp t rp t rp t rp t rp t rp t rp begin auto- precharge bank b begin auto- precharge bank a begin auto- precharge bank b begin auto- precharge bank a begin auto- precharge bank b begin auto- precharge bank a begin auto- precharge bank b begin auto- precharge bank a begin auto- precharge bank a begin auto- precharge bank b begin auto- precharge bank b activate command bank b read bank b with auto- activate command bank a activate command bank b activate command bank a activate command bank b activate command bank a activate command bank b activate command bank a activate command bank b activate command bank a activate command bank b activate command bank a precharge read bank a with auto- precharge read bank b with auto- precharge read bank a with auto- precharge read bank b with auto- precharge read bank a with auto- precharge read bank b with auto- precharge read bank a with auto- precharge read bank b with auto- precharge read bank a with auto- precharge read bank b with auto- precharge discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 108 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm full page random column read t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 2 a0 - a9 t ck2 activate command bank a rax rax rbx cax cbx cay rbx activate command bank b read command bank a read command bank b read command bank a caz read command bank a cby read command bank b cbz read command bank b precharge command bank b (precharge termination) ax0 ay1 ay0 bx0 by0 az1 az0 by1 az2 bz2 bz1 bz0 t rrd t rcd activate command bank b rbw rbw t rp discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 109 of 120 \ clk cke cs dq ras cas we a11(bs) dqm full page random column write t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 2 a0 - a9 t ck2 activate command bank a rax rax rbx cax cbx cay rbx activate command bank b write command bank a write command bank b write command bank a caz write command bank a cby write command bank b cbz write command bank b precharge command bank b (precharge termination) dax0 day1 day0 dbx0 dby0 daz1 daz0 dby1 daz2 dbz2 dbz1 dbz0 t rrd t rcd write data is masked activate command bank b rbw rbw t dpl t rp discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 110 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm precharge termination of a burst (1 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = full page, cas latency = 1 a0 - a9 t ck1 rax rax cax write command bank a activate command bank a precharge command bank a dax0 dax4 dax3 dax2 dax1 precharge termination of a write burst. write data is masked. ray ray cay activate command bank a read command bank a ay0 ay1 ay2 precharge termination of a read burst. precharge command bank a activate command bank a write command bank a daz0 daz3 daz2 daz1 t rp t rp daz4 daz7 daz6 daz5 raz raz caz discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 111 of 120 \ clk cke cs dq ras cas we a11(bs) dqm precharge termination of a burst (2 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 t ck2 precharge command bank a dax0 dax3 dax2 dax1 precharge termination of a write burst. write data is masked. ay0 ay1 ay2 precharge termination of a read burst. precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz caz read command bank a az0 az1 az2 precharge command bank a t rp burst length = 8 or full page, cas latency = 2 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 112 of 120 08j3348.e35853 5/98 \ clk cke cs dq ras cas we a11(bs) dqm precharge termination of a burst (3 of 3) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 burst length = 4,8 or full page, cas latency = 3, t rcd ,t rp = 3 a0 - a9 t ck3 precharge command bank a dax0 precharge termination of a write burst. write data is masked ay0 ay1 ay2 precharge termination precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz of a read burst. dax1 ay3 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 113 of 120 \ clk cke cs dq ras cas we a11(bs) dqm cs function (only cs signal needs to be asserted at minimum rate) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 at 100mhz burst length = 4, cas latency = 3, t rcd, t rp = 3 a0 - a9 t ck3 rax low rax cax cay read command bank a write command bank a activate command bank a precharge command bank a ax0 day0 day3 day2 day1 ax3 ax2 ax1 t rcd t dpl discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 114 of 120 08j3348.e35853 5/98 note: all dimensions are in millimeters; package diagrams are not drawn to scale. package dimensions (400mil; 44 lead; thin small outline package) lead #1 0.80 basic 0.35 10.16 0.13 18.41 0.13 11.76 0.20 - 0.05 + 0.10 0.805 ref detail a 0.10 seating plane detail a 0.25 basic gage plane 0.5 0.1 0.05 min 1.20 max discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 115 of 120 note: all dimensions are in millimeters; package diagrams are not drawn to scale. package dimensions (400mil; 50 lead; thin small outline package) lead #1 0.80 basic 0.35 10.16 0.13 20.95 0.13 11.76 0.20 - 0.05 + 0.10 0.125 0.875 ref detail a 0.10 seating plane +0.075 -0.005 detail a 0.25 basic gage plane 0.5 0.1 0.05 1.20 max +0.10 -0.00 1.00 0.05 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 116 of 120 08j3348.e35853 5/98 note: all dimensions are in millimeters; package diagrams are not drawn to scale. package dimensions (400mil; 44 lead; 2 high stack; thin small outline j lead package) lead #1 lead #1 identifier (1.27) 0.8 0.8 0.3 + 0.10 - 0.04 0.5 seating plane 0.10 0.75 min 3.20 max 11.4 0.25 10.15 9.90 0.40 + 0.13 - 0.04 18.40 0.28 discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 117 of 120 revision log revision contents of modi?cation 2/10/97 initial release (preliminary) 5/16/97 page 20 correction to auto-precharge description/diagram notes. (page 23, 24) page 50 change t dpl from 8ns to 10ns for -10. page 67 correct cke transition. page 45 correction of note regarding total stack current (cbr current). 7/14/97 page 25 precharge termination changed (now similar to burst stop). page 26 page 29 page 30 page 66 correct we - read command. page 70 precharge termination changed: precharge and subsequent commands 1 clock sooner. page 70 correct a10 - precharge command a. page 87 precharge termination changed: last precharge 1 clock sooner. page 95 fix numbering of data - address az. page 96 fix numbering of data - address az. page 98 correct a10 - read command. page 101 correct a10 - first write command. page 110 correct a10 - write and read commands. page 112 precharge termination: number of data bits after command changed. page 115 precharge termination: number of data bits after command changed. 8/21/97 page 45 add note to i cc2 ns. discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 118 of 120 08j3348.e35853 5/98 10/08/97 page 1 remove -7, -8; add -322, -90. remove low power sr. change max. data rate. page 2 remove v ref , remove part numbers. page 3 page 4 remove v ref . page 5 change part number information. page 6 remove v ref . (also, page 7 - page 9.) page 10 remove v ref in power on description. page 14 change max. data rate. page 43 remove sstl_3 recommended dc operating conditions. page 44 remove sstl_3 output characteristics. page 45 change currents - different speed sorts. page 46 change currents - different speed sorts. page 48 remove -7, -8; add -322, -90. page 49 page 50 page 51 change speed sorts. page 55 correct address (page 55 also). 11/14/97 page 1 remove x8 stack. add column address clarification. add note to performance table. page 3 remove x8 stack. page 5 update ordering information. page 9 remove x8 stack. page 22 change diagrams. page 26 change/ add diagram. page 28 change diagram. page 30 change/ add diagram. page 31 change text (t dpl ) . page 32 change diagram/ text (t dpl ) . page 45 specify -322 i cc2p , i cc4 currents. page 48 change notes for ac characteristics and clock and clock enable parameters tables (v ih , v il , t t ) . page 52 correct/ clarify titles. page 71 add timing diagram: random column read, cl=3, t rcd / t rp = 2 . page 75 change diagram. page 91 page 115 revision log discontinued (12/98 - last order; 9/99 last ship)
ibm0316409c ibm0316809c ibm0316169c IBM03164B9C 16mb synchronous dram-die revision d 08j3348.e35853 5/98 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 119 of 120 1/05/98 page 1 update speed sort information: remove -90, add -80. also, page 5, page 14, page 45, page 46, page 48 - page 51. page 21 update auto-precharge description. page 22 add diagrams showing auto-precharge interrupt. also, page 23, page 24. page 26 change -90 to -80 or add -80. also, page 28, page 30. page 35 update power down mode description. also, page 37. page 39 update read/write with auto-precharge notes. page 67 correct address inputs. page 74 add t dpl clarification. also, page 75, page 90, page 91, page 115. 2/2/98 change -322 to -360. 2/23/98 page 45 change i cc2p (2ma->3ma), i cc4 (400 m a->2 ma), for -360 sorts. 3/13/98 page 5 add 1mx16,-80. page 46 remove currents for -360 (x4, x16). only x8 supported. page 49 update t hz . 5/1/98 page 49 add clarification: t oh . revision log discontinued (12/98 - last order; 9/99 last ship)
intern ational business machines corp.1998 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a discontinued (12/98 - last order; 9/99 last ship)

▲Up To Search▲

Price & Availability of IBM03164B9C

	To Download IBM03164B9C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .